Recently, demand for improved quality of silicon (Si) single crystal wafers have been escalated due to high integration of devices. Herein, the improved quality means being free from defects in a device operation region. Many of conventional largely fabricated devices such as memories or logics operate in the vicinity of the surface of the wafer, and accordingly the vicinity of the surface has been made to be defect-free. These can be achieved by a wafer such as an epitaxial wafer, an anneal wafer, a PW (polished wafer) cut out from a defect-free crystal.
However, power devices are gaining attention recently in view of energy saving. When this device is made of Si crystal, there increases a case in which electricity is conducted in the direction of thickness of a wafer in order to conduct a large amount of electricity. Accordingly, it needs to annihilate defects not only in the vicinity of the surface, but also in the interior of a wafer. In order to achieve this, it is possible in epitaxial wafers to make the thickness of epitaxial layers equivalent to the thickness used as a device, for example. However, this is very expensive and unpractical. Accordingly, it is effective to grow a crystal free from grown-in defects and to cut out a wafer from the defect-free crystal which is entirely defect-free.
As grown-in defects, two types are known including a void defect of a vacancy type in which an Si atom at a lattice point is lacking and a dislocation cluster defect of an interstitial-Si (inter-lattice Si, hereinafter also referred to as I-Si) type in which an Si atom is interposed into a lattice. The state of forming the grown-in defects differs due to a growth rate of a single crystal or a cooling condition of a single crystal pulled from a silicon melt.
It is known that, for example, when a single crystal is grown by setting the growth rate relatively large, the vacancy type is predominant. The vacant defect formed by aggregation of this vacancy is called a void defect, and is detected as an FPD (Flow Pattern Defect), a COP (Crystal Originated Particle), or an LSTD (Laser Scattering Tomography Defect), although the name differs with the detecting method. It is considered that when these defects are introduced to an oxide film formed on the silicon substrate, for example, the electrical properties are degraded to cause a breakdown voltage failure of an oxide film and so on.
On the other hand, it is known that when a single crystal is grown by setting the growth rate relatively small, the I-Si is predominant. On an aggregation of this I-Si, an LEP (Large Etch Pit=dislocation cluster defect) is detected, in which the LEP is considered to be formed by clustering of a dislocation loop. It is said that when a device is formed on a region in which this dislocation cluster defect can be generated, a serious failure such as a current leakage occurs.
Accordingly, it is possible to obtain a defect-free region, in which a vacancy or I-Si is not contained or contained in a small amount so as not to form a void defect or a dislocation cluster defect, when a crystal is grown in an intermediate condition between the condition in which the vacancy is predominant and the condition in which the I-Si is predominant. As a method to obtain such a defect-free crystal, it has been proposed a method to control the temperature in a furnace or the growth rate as described in Patent Document 1. However, there is a problem of relatively low productivity since defect-free crystals generally have low growth rate.
There are various means to find a defect-free region in a CZ crystal, and one of them is an oxide precipitate. This is due to oxygen in a CZ silicon crystal to form oxide precipitate (SiO2) through a heat treatment. The oxygen precipitation reaction has a tendency to be promoted under an existence of vacancy, and accordingly the oxide precipitate generates differently due to a defect region. This is utilized to find a defect region.
Recently, low oxygen products are highly demanded in various devices such as memories and logics as well as power devices and RF devices. This is because oxygen changes to a donor through a low temperature heat treatment to change the resistivity. Another reason is improving cleanliness of device processes, which does not require conventional gettering technology of heavy metal impurities by forming oxide precipitates in a wafer. On the other hand, the low oxygen concentration causes a problem in which the foregoing defect evaluation by oxide precipitates is difficult, thereby making it difficult to find a defect-free region.
One of the means to solve the foregoing problem in defect-free crystals is to grow a crystal in a vacancy-rich region, where the growth rate can be large. In this region, however, vacancies aggregate to generate a void defect. Accordingly, several technologies to annihilate these void defects has been disclosed previously.
Patent documents 2 and 3 disclose technologies to annihilate void defects by a non-oxidizing heat treatment and oxidation heat treatment. In these technologies, a non-oxidizing heat treatment is performed first so as to cause out-diffusing of oxygen in the vicinity of a wafer surface to dissolve inner wall oxide films of the inner-walls of vacant void defects. Then, an oxidation heat treatment is performed to implant I-Si from an oxide film formed on the surface into the interior of a wafer to fill void defects. Patent document 4 discloses a technology of an oxidation heat treatment and a non-oxidizing heat treatment, in which the order of the processes are reversed.
These technologies can annihilate void defects. These technologies, however, require two-step heat treatments, which causes high cost. As another problem, they can only eliminate void defects in the vicinity of a surface.
In addition, Patent Document 5 discloses a method of oxidation heat treatment at 1,300° C. This is a one-step heat treatment, but the temperature of 1,300° C. increases the difficulty, and causes problems of contamination of a water or generation of slip dislocation.
In the foregoing technologies, an influence of the oxygen concentration is not clarified. The influence of the oxygen concentration is described in Patent Document 6, for example. This technology increases the forms in which plural of void defects are linked together, and makes it easier to annihilate the void defects by a heat treatment thereby. In this technology, however, a non-oxidizing heat treatment is performed. This recommends to increase the oxygen concentration or reduce the cooling rate, which are contrary to an oxidation heat treatment described below.
On the other hand, Patent Document 7 discloses that void defects are annihilated only by treating at a relatively low temperature of 1,200° C. or less in an oxidation heat treatment when the oxygen concentration is low, and it is a known technology. This can be reasoned that the solid solubility limit (equilibrium concentration) of oxygen in a silicon crystal is approximately 8 ppma-JEIDA at 1,200° C., for example. When an oxygen concentration is lower than that, it is considered that inner wall oxide films of voids can be dissolved even when a non-oxidizing heat treatment is not performed unlike the foregoing Patent Document 2 and 3. At the same time, an oxide film is formed on the surface and I-Si is implanted, and accordingly it is possible to annihilate voids only by an oxidation heat treatment without requiring any particular process.
Applying this technology, Patent Document 8 discloses a technology to annihilate void defects by an oxidation heat treatment on a silicon wafer with low oxygen concentration. Patent Document 8, however, does not describe a void defect size. Patent Document 9 discloses a similar technology and describes the void size. However, the size is as large as 100 nm, and the dependence on a size is not mentioned. As described later, void defects are not fully annihilated by an oxidation heat treatment when the void size is large. Accordingly, these technologies cannot fully annihilate void defects. Moreover, the both of these technologies target for articles irradiated with neutron. The treatment temperature is relatively high and the treatment time is relatively long, which are considered to combine a recovery heat treatment. Accordingly, they have a problem regarding cost reduction, and also have problems of wafer contamination or generation of slip dislocation.